(For a detailed tour, please read the tutorial)

Here’s a simple state machine:

This can generate any of the following by changing a single switch on the command line:

Verilog, encoded

Verilog, one-hot

SystemVerilog, encoded

SystemVerilog, one-hot

It is also possible to generate VHDL, but you must enter the transition equations in VHDL syntax:

VHDL, encoded

VHDL, one-hot