module cliff_classic (
output wire ds,
output wire rd,
input wire clk,
input wire go,
input wire rst_n,
input wire ws
);
parameter
IDLE = 3'b000,
DLY = 3'b010,
DONE = 3'b001,
READ = 3'b110;
reg [2:0] state;
reg [2:0] nextstate;
always @* begin
nextstate = 3'bxxx;
case (state)
IDLE: begin
if (go) begin
nextstate = READ;
end
else begin
nextstate = IDLE;
end
end
DLY : begin
if (ws) begin
nextstate = READ;
end
else begin
nextstate = DONE;
end
end
DONE: begin
begin
nextstate = IDLE;
end
end
READ: begin
begin
nextstate = DLY;
end
end
endcase
end
assign ds = state[0];
assign rd = state[1];
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
state <= IDLE;
else
state <= nextstate;
end
`ifndef SYNTHESIS
reg [31:0] statename;
always @* begin
case (state)
IDLE:
statename = "IDLE";
DLY :
statename = "DLY";
DONE:
statename = "DONE";
READ:
statename = "READ";
default:
statename = "XXXX";
endcase
end
`endif
endmodule